Low-complexity Multi-Bit Iterative Decoders: Algorithms and Hardware Architectures

We present a new type of iterative decoders for low-density parity check (LDPC) codes that use simple Boolean functions for variable node processing and surpass the belief propagation decoders in the error floor region. We discuss the error performance, guaranteed error correction capability and speed and implementation complexity of these decoders as factors crucial for application that require extremely high high speeds. We also present a hardware architecture and show that our decoders require only half an silicon area to achieve the same throughout as best efficient min-sum decoders, while improving the frame error performance in the error floor region.